Semiconductor devices are employed in various systems for a wide variety of application. Device fabrication typically involves a series of process steps including layering material on a semiconductor substrate wafer, patterning and etching one or more of the material layers, doping selected layers and cleaning the wafer.
Semiconductor manufacturers continually seek new ways to improve performance, decrease cost and increase capacity of semiconductor devices. Capacity and cost improvements may be achieved by shrinking device size. For example, in case of trench devices, e.g, such as capacitors and transistors, more and more cells can fit onto the chip without loosing device performance by enlarging the aspect ratio of the cells, e.g., reducing the diameter/and or enlarging the depth of the cells. With regard to trench capacitors the size reduction results in greater memory capacity for the chip or higher possible specific capacities (capacity per chip area). Cost reduction is achieved through economies of scale. Unfortunately, semiconductor manufacturing gets more and more difficult when device component size is reduced. Therefore, it is a challenge to balance cost reduction by size reduction (shrink) with other manufacturing constrains.